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- Well...this program should show that certain people either
- spread misinformation on purpose or just don`t know it better.
- To measure the memory *BUS* performace and NOT the CPU
- performance you have to understand how the cache works.
-
- For CopyBack mode:
- If you measure the WRITE bus performace you have to subtract
- the LINE prefetch.
- If you measure the READ bus performance you shouldn`t measure
- the CPU's own cache controller latency as you would do with
- something like that:
-
- ;gpr3=LINE start
- lwz gpr4,0(gpr3) ;stall until this word is in the cache
- lwz gpr5,4(gpr3) ;stall until this word is in the cache
- lwz gpr6,8(gpr3) ;stall until this word is in the cache
- lwz gpr7,12(gpr3) ;stall until this word is in the cache
- lwz gpr8,16(gpr3) ;stall until this word is in the cache
- lwz gpr9,20(gpr3) ;stall until this word is in the cache
- lwz gpr10,24(gpr3) ;stall until this word is in the cache
- lwz gpr11,28(gpr3) ;stall until this word is in the cache
- ..basicly you measure the LINE read + CPU Cache stalls.
-
-
- Correct would be
- lwz gpr4,0(gpr3) ;stall until this word is in the cache(hides line read)
- lwz gpr5,32(gpr3) ;stall until this word is in the cache
- ;and that`s after the last line is read(hides line read)
- lwz gpr6,64(gpr3) ;stall until this word is in the cache
- ;and that`s after the last line is read(hides line read)
- lwz gpr7,96(gpr3) ;stall until this word is in the cache
- ;and that`s after the last line is read(hides line read)
-
- this in continues memory and with a greater loop. Then these
- accesses are in pipeline so it doesn`t matter that the last
- lwz gpr7 returns before the line is read complete.
-
-
- For non COPYBACK modes the situation looks
- different.
-
-
- The Cache Speed test is disabled because it doesn`t work
- reliable(yet).
-
- P.S.
- Source is provided to avoid another conspiracy thread.
-